Complementary metal oxide semiconductor (CMOS) devices are well-known in the semiconductor art. This class of device employs n channel transistors (NMOS) and p channel transistors (PMOS) in circuit configurations that have many superior qualities that are well appreciated. In conventional CMOS products operation is usually specified over the voltage range of 3 to 15 volts. However, the circuits can commonly operate up to 18 volts. These are referred to as high voltage devices. In order to increase circuit density for improved utilization of integrated circuit (IC) chip area, device spacings have been reduced to a minimum to create a new class of devices known as high density, low voltage CMOS. These devices normally have an upper voltage limit of about 7 volts.
The physical differences can readily be seen in U.S. Pat. No. 3,983,620 which issued to Gregorio Spadea on Oct. 5, 1976, and is assigned to the assignee of the present invention. This patent discloses a number of CMOS structures. FIG. 15 illustrates, in cross section showing, a high voltage structure. FIG. 19 shows a similar low voltage structure. It can be seen so that the major difference is that in the low voltage construction, the space between N+ guard rings and the P+ regions has been eliminated. This results in a voltage limit defined by the zener voltage of the P+ to N+ junctions.
While the high density construction has an upper voltage limit of about 7 volts, this is not ordinarily a problem. In terms of low voltage limits the constraints are conventional. The lowest operating limit is established by the higher of the thresholds of the PMOS and NMOS devices. The optimum operating voltage is equal to the sum of the thresholds for the PMOS and NMOS devices (hereafter to be referred to as sum of thresholds). At this voltage, the CMOS inverters operate at maximum speed-power product and gain. Clearly operation at sum of thresholds is desirable, but this value varies substantially in the device manufacturing process. One approach is to use an operating voltage sufficiently high to exceed sum of thresholds for worst case device tolerances. Alternatively, a voltage regulator is employed to power the circuit and the regulator is supplied with a reference voltage developed by sensing the sum of thresholds for on-chip p and n channel devices. The regulator then maintains the voltage across the low voltage section at its optimum value. As the transistor threshold values vary, as a result of the inevitable variations encountered in IC manufacture, such a regulator will automatically produce the desired voltage.
The prior art has recognized the usefulness of the constancy of a transistor threshold for use as a voltage regulator reference. However, most of the prior art circuits employ all p channel or n channel devices. Other prior art examples, such as U.S. Pat. No. 4,061,962, employ other semiconductor devices such as pn junction diodes in their circuits and commonly reference the regulated voltage to V.sub.SS or ground. For example, in U.S. Pat. No. 4,128,816, a junction diode and a bipolar transistor are employed to translate a threshold reference value. In other approaches, such as the one in U.S. Pat. No. 4,100,437, a voltage regulator uses a transistor threshold as a reference, but employs level shifting to obtain a regulated voltage of the desired magnitude.